The present invention relates to the fabrication of integrated circuits, and more particularly, to the deposition and etching of dielectric layers on a substrate as well as planarization of damascene interconnects.
As device dimensions continue to shrink it becomes more challenging to prevent the interconnect delay from limiting the overall chip performance. One solution is to introduce new dielectric materials with a lower dielectric constant. Ultra Low K (ULK) dielectrics have a dielectric constant of about 2.5 or less and offer a significant advantage by lowering the capacitive coupling between interconnects and in turn lowering the interconnect delay. The integration of ULK dielectrics, however, presents numerous challenges and incompatibility of ULK dielectrics with Chemical Mechanical Polishing (CMP) is one example.
The retention of the hardmask layer is therefore becoming an important constraint for the integration of some ULK dielectrics. It assures that the ULK dielectric remains intact and free of defects without modification of the dielectric constant. To maintain sufficient hardmask coverage in all areas the hardmask layer will need to be relatively thick. Since a typical hardmask has a dielectric constant of 3.0 or more, a thicker hardmask adversely affects keff and Ctotal. (Ctotal is the capacitance of an interconnect and includes the capacitive coupling to all its neighboring interconnects. Keff is the dielectric of a single medium that would yield the same Ctotal if it were to replace all the dielectric films between the interconnects.) The hardmask can also serve the purpose of etch stop during the via etch of subsequent levels thereby ensuring that exposed interlevel dielectric (ILD), in the case of misaligned vias, is not affected.
Current problems in the art include the loss of hardmask due to CMP in areas that have a high metal to dielectric ratio, typically 85%, and hardmask retention problems in areas with underlying topography. Increased hardmask thickness requirements due to CMP selectivity of these features lead to overall higher line to line capacitance. Another problem is inability to retain hardmask leads to ULK damage, causing reliability failures such as Cu nodule accumulation, Cu corrosion and low voltage breakdown due to poor adhesion and voids.
The present invention describes a new integration scheme which relies on a thin embedded barrier to prevent exposure of ULK material during or after CMP. The thin embedded film serves both purposes of the hardmask without being susceptible to CMP related hardmask retention issues. The layer is thin enough to protect the ULK during CMP and subsequent via etch without adversely affecting the keff and Ctotal.
The invention also provides a novel structure. The invention uses a combination of an embedded film, etchback, using either selective CoWP or a conformal cap such as a SiCNH film, to ensure that the ULK material is never exposed to the CMP process or to the via etch, clean and liner deposition of the next interconnect level.
These and other purposes of the present invention will become more apparent after referring to the following description in conjunction with the accompanying drawings.